www.fairchildsemi.com ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 AN-6961 critical conduction mode pfc controller description this application note describes a power factor correction (pfc) circuit using the fan6961. both the features of this controller, as well as the operation of the power factor correction circuit, are presented in detail. based on the proposed design guideline, a design example with detailed parameters demonstrates the per formance of the controller. introduction the fan6961 pfc controller is an 8-pin boundary current mode (bcm) ic intended for controlling pfc pre-regulators. the fan6961 provides a controlled on-time to regulate the output dc voltage and achieve natural power factor correction. the maximum on-time of the switch is programmable to ensure safe operation during ac brownouts. an innovative multi-vector error amplifier is built in to provide rapid transient response and precise output voltage clamping. once the output feedback loop is opened, the output driver (gd) is disabled to provide protection of the system. the start-up current is lower than 20a and the operating current has been reduced to 5ma. the supply voltage can be operated up to 25v, maximizing application flexibility. the fan6961 also enables cycle-by-cycle current limiting protection for the external power mosfet. figure 1. power factor correction circuit
AN-6961 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 2 basic operation of the boost converter the typical boost converter and its operational waveforms are shown in figure 2, 3, and 4, respectively. () g vt + ? () l vt +? d co r o o v + ? () l it q b l figure 2. boost converter () g vt + ? () l vt +? () l it q b l () g vt + ? () l vt +? co r o o v + ? () l it b l (a) switch q is on (b) switch q is off figure 3. switching sequences of the boost converter () og b vvt l ? () l vt on t off t q () l it () g b vt l () g vt g () o vvt ? t , (t) lavg i figure 4. one-cycle waveform of the boost converter operation principle switch q is on: when q turns on, the rectifier diode d is reverse-biased and output capacitor c o supplies load current. the rectified ac line input voltage v g (t) is applied to the inductor l b so that inductor current i l ramps up linearly and can be expressed as: b g on l l (t) v t i = ) ( (1) switch q is off: when q turns off, the voltage v o -v g (t) is applied to inductor l b and the polarity on the inductor l b is reversed. the diode d is forward-biased in this stage. the energy stored in the inductor l b is delivered to supply load current and output capacitor c o . the inductor current i l can be expressed as: b g o off l l (t) v - v t i = ) ( (2) controlled on-time: the on-time of the power mosfet q is determined by the output of the error amplifier that monitors the preregulator output voltage. with a low- bandwidth error amplifier, the feedback signal is almost constant during a half ac cycle, resulting a fixed on-time of the power mosfet at a specific ac voltage and some certain output power level. therefore, the peak inductor current i lpk automatically follows the input voltage v g (t), achieving a natural power factor correction mechanism. figure 5 shows the typical inductor current waveform during a half ac cycle. on off , () lavg it () g vt max t gate , lpk i min t - f ixed on time figure 5. controlled on-time inductor current waveform referring to figure 4, considering one switching period the average inductor current i l,ave (t) can be calculated by the average area of triangle waveform of inductor current: s 2 b s on g t l 2 t t ) t ( v ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = (t) v - v (t) v t i g o 2 g avg l, (3)
AN-6961 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 3 block operati on description multi-vector error amplifier the fan6961 has a trans-conductance type amplifier that provides better dynamic perform ance. referring to figure 6, the error amplifier output v ea is compared with a sawtooth waveform to generate a fixed on-time. to achieve a low input current thd, the variation of the on-time within one input ac cycle should be very small. therefore, the bandwidth of the feedback loop should be set below 20hz to maintain a constant on-time for a line half-cycle. connecting a capacitance c ea , such as 1f, between comp and gnd is suggested. t _ ea out v pwm gate ds v () l it t t t () g b vt l -() og b vvt l on t sawtooth generator () g vt off t figure 6. operation waveforms of fixed on time technique for fast transient response and precise clamping of the output voltage overshoot and undershoot, the fan6961 has a built-in multi-vector error amplifier. figure 7 shows the block diagram of the multi-vector error amplifier. when the variation of the feedback voltage exceeds +6% and -8% of the reference voltage, the multi-vector error amplifier adjusts its output impedance to increase the loop response. 1 2 fan6961 2.65v 2.3v inv c o v o v ref (2.5v) v ea_out c ea comp error amplifier figure 7. block diagram of the multi-vector error amplifier total harmonic distortion (thd) optimization as discusses previously, the fan6961 uses the controlled on-time technique to achieve power factor correction mechanism. however, to get better thd at light load condition, especially at high input voltage, a thd optimization circuit is inserted into the fan6961. with this internal thd optimization circuit, the on-time of the power mosfet is modulated to further improve the thd performance. the calculated on-time variation within one line voltage period with the fixed on-time technique, and after the thd optimization is added, are shown in figure 8. the calculated input current waveform is shown in figure 9. 5.00e-07 2.50e-06 4.50e-06 6.50e-06 8.50e-06 1.05e-05 1.25e-05 1.45e-05 1.65e-05 1.85e-05 0 20 40 60 80 100 120 140 160 time(s/10000) turn on time(s) thd optimization(vac=90v,vo=250v) fixed on time(vac=90v,vo=250v) thd optimization(vac=264v,vo=400v) fixed on time(vac=264v,vo=400v) figure 8. mos turn-on time calculational curve (before and after thd optimization circuit added) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 20 40 60 80 100 120 140 160 time(s/10000) current(a) thd optimization(vac=90v,vo=250v) fixed on time(vac=90v,vo=250v) thd optimization(vac=264v,vo=400v) fixed on time(vac=264v,vo=400v) figure 9. calculated waveforms of the input current (before and after thd optimization circuit added)
AN-6961 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 4 figure 10 shows the measured input current on the example circuit board . ch2: before thd optimization (1a/div); ref1: after thd optimization (1a/div) figure 10. calculated waveforms of the input current (before and after thd optimization circuit is added) figure 11 shows the measured thd performance on the example circuit board. 2 3 4 5 6 7 8 9 10 90 110 220 240 264 vac(v) thd(%) thd optimization fixed on-time figure 11. measured thd result at full load condition (fixed on-time technique vs. thd optimization) over- / under-voltage protection (ovp/uvp) over / under-voltage protection is built-in to provide protection by detecting and examining the voltage on inv pin. when the voltage v inv exceeds 2.75v due to abnormal conditions, the internal ovp prot ection circuit is triggered to disable the pwm output. over-voltage conditions are usually caused by an open-loop feedback. a debounce time around 35 s is added to prevent false triggering. if the voltage v inv is below 0.45v due to short-circuit conditions, pwm output is turned off. 1 2 figure 12. block diagram of the over / under- voltage protection zero-current detection figure 13 shows the block diagram of the zero-current detection. the zero inductor current detection is performed by sensing the information on an auxiliary winding of the pfc inductor. as shown in figure 14, when q turns off, the stored energy of the inductor starts to release to the output. the voltage on the zcd starts to decrease when the energy in the inductor dries out. once the zcd voltage is lower than the threshold voltage (1.75v typical), the pwm output is high again and initiates a new switching cycle. the output rectifier is always turned off with zero current, so the converter works in boundary mode conditions and the power mosfet is switched on with low voltage to minimize the switching losses. once the zcd voltage is lower than the disable threshold voltage (around 0.25v) for a duration of about 800s, the pwm output is disabled. to prevent high switching frequency during light load conditions, an inhibit timer function is built in to limit the maximum switching frequency. an rc filter (c zcd is around 0~22pf, r zcd is around 33k~68k ) connected from auxiliary winding to the zcd pin is recommended to improve noise immunity on the zcd pin. figure 13. block diagram of the zero-current detection
AN-6961 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 5 10v 2.1v 1.75v v o v g (t) v zcd v ds gate 2v g (t) - v o inhibit time t t t figure 14. v ds & v zcd & gate waveform maximum on-time operation the on-time of the power mosfet is varied with the output power and the ac input voltage. while the ac input voltage decreases, the on-time increases accordingly. the maximum on-time limit t on,max can be programmed by the resistor connected between mot and gnd pin. ) s ( 24 25 ) k ( r mot ? = max on, t (4) the range of the maximum on-time is designed to be within 10~50 s; 25 s is recommended. v cc over-voltage protection a v cc over-voltage protection avoids damage when the voltage v dd exceeds the internal threshold due to an open- loop failure. once the protection is triggered, the pwm output is turned off. peak current limiting the switch current is sensed across a resistor and supplied to an input terminal of a comparator. a voltage higher than the 0.82v threshold voltage on the cs pin immediately terminates the current switching cycle, activating cycle-by- cycle current limiting. leading-edge blanking (leb) a turn-on spike inevitably occurs at the cs pin when the power mosfet is switched on. at the beginning of each switching pulse, the current-limit comparator is disabled for around 350ns to avoid premature termination. the gate drive output cannot be switched off during the blanking period. under-voltage lockout (uvlo) the turn-on and turn-off threshold voltages are fixed internally at 12v and 9.5v, respectively. this hysteresis behavior guarantees a one-shot start-up, as long as a proper start-up resistor and hol d-up capacitor are used. output driver with a low on resistance and a high current driving capability, the output driver c an drive an external capacitive load larger than 3000pf. cross conduction currents are avoided to minimize heat dissipation, improving efficiency and reliability. this output driver is internally clamped by a 17v zener diode. lab note before rework or solder/desolder on the power supply, discharge the primary capacitors by external bleeding resistor . otherwise, the pwm ic may be destroyed by external high voltage during solder/desolder. design guideline pfc inductor design as shown in figure 15, considering one ac line voltage cycle, the minimum switching frequency f s,min occurs at the peak of the ac line voltage. to avoid audible noise, the minimum switching frequency f s,min must be above audible frequency. the appropriate inductance can be calculated by equation 5. the minimum switching frequency f s,min may happen in ac maximum or minimum input voltage, depending on the output voltage. therefore, calculate both the maximum and the minimum input voltages, then choose the lower inductance value. ( ) min . s o o pk o 2 pk f v p 4 v v v ? ? ? ? ? ? = b l (5) where: l b is the pfc inductor, is conversion efficiency, v pk is the peak of the ac line voltage, p o is rated output power, v o is pfc output voltage, f s ,min is the minimum switching frequency. 0.00e+00 1.00e+04 2.00e+04 3.00e+04 4.00e+04 5.00e+04 6.00e+04 7.00e+04 0 1020304050607080 time(s/5000) switching frequency(hz) switching frequency line input voltage[vin(t)*200] figure 15. frequency vs. input voltage the peak inductor current i lpk can be expressed as: ? ? ? = min . rms o v 2 p 4 l,pk i (6) where v rms.min is the minimum input line rms voltage. with the internal thd optimization circuit, the real peak inductor current is smaller than calculated. usually, the real peak current is around 95% of calculated value.
AN-6961 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 6 determine current-sense resistor the mosfet on-time and the input current increase with the decreasing ac input voltage or increasing load. the fan6961 can establish the maximum on-time limit (25s is recommended) of power mosfet. once the voltage on current-sense pin reaches the internal limit v cs , 0.82v typically, the fan6961 stops the pwm output immediately. thus, the maximum output power can be designed by the current-sense resistor and maximum on-time limit. in general operation, the maximum on-time occurs at minimum ac input voltage and maximum loading conditions. when the output power increases from full load to maximum load, the on-time is restricted to the maximum on- time limit first, then the current limit. in the design example, the voltage on the current-sense pin is set to 0.57v at full load and minimum input voltage conditions. at this condition, the maximum power is about 156% of full load at minimum input voltage condition. the current-sense resistor can be calculated from equation 7. the calculated curve of the mosfet turn-on time at different loading conditions are shown in figure 16. the calculated waveforms of the pfc inductor current at two kinds of current limit are shown in figure 17. 1.00e-05 1.20e-05 1.40e-05 1.60e-05 1.80e-05 2.00e-05 2.20e-05 2.40e-05 2.60e-05 0 35 70 105 140 175 210 245 280 315 time(s/20000) turn on time(us) full load pin=105.9w 110% full load pin=116.46w 120% full load pin=127w 150% full load pin=158.8w max. pin=164.7w (0.82 /4.55a) current sense limit v . - (25 ) max on time limit us figure 16. calculated curve of the mosfet turn-on time at different loading conditions 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 0 35 70 105 140 175 210 245 280 315 time(s/20000) pfc inductor current(a) max. pin=164.7w,current limit=4.55a max. pin=140.4w,current limit=3.727a 150% full load pin=158.8w, current limit=4.55a (3.727 ) 0.7 . 133% current limit a full load vcs v max load full load = (4.55 ) 0.57 . 156% current limit a full load vcs v max load full load = figure 17. calculated waveforms of the pfc inductor current at two current limits 95% i 0.57 r pk l, s ? = (7) the fan6961 current-sense limit, v cs , is 0.82v typically. from faraday?s law, the number of turns for pfc inductor can be obtained by: 6 e max pk , l b b 10 a b i l n ? ? ? = (8) where: a e is the effective area of the core-section, b max is saturation magnetic flux density. determine the auxiliary winding the fan6961 can perform zero-current detection by sensing the information on an auxiliary winding of the pfc inductor. as discussed previously, when the zcd voltage is lower than the threshold voltage (1.75v typical), the pwm output is high again and initiates a new switching cycle. however, there is a prerequisite: the zero-current detector voltage must exceed the rising-edge threshold voltage (2.1v typical) before it falls below 1.75v. the minimum rising- edge voltage of zero-current detector input occurs at the peak of the highest ac line voltage, which is equal to n / v 2 - v max rms, o ? and must be larger than the zcd input rising-edge threshold voltage (2.1v typical). the zcd voltage v zcd should be established as high as 120% of 2.3v to have a safe margin; therefore, the number of turns for auxiliary winding is obtained as: b max . rms o zcd aux n v 2 v 2 . 1 v ? ? ? ? = n (9) where v rms,max is the maximum input line rms voltage. v zcd is the rising-edge voltage of zero-current detector input. :1 n figure 18. simplified power stage calculate on-time t on.fix the fixed on-time for the specific output power, inductor, and input voltage can be calculated by: ? ? ? = 2 rms b o fix . on v l p 2 t (10) where: l b is the pfc inductor, is conversion efficiency, p o is the maximum rated output power, v rms is the input line rms voltage.
AN-6961 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 7 determine the output capacitor c o the output capacitor is determined by the requirement of sufficient hold-up time t hold : ? ? ? ? ? ? ? ? ? ? = 2 min . o 2 o hold o o v v t p 2 c (11) where t hold is the output capacitor hold-up time, which is measured from the time the ac input turns off to before the output voltage falls below the minimum operating voltage of the following dc/dc stage. the output ripple voltage v o is expressed as: o o o o v c p v ? ? = (12) where: = 2 f, f is ac line frequency, i o is the output current. determine the compensation capacitor c ea as discussed previously, to achieve a low input current thd, the variation of the on-time within one input ac cycle should be very small. to achieve this, the bandwidth should be lower than 20hz. the capacitance c ea connected between comp and gnd can be obtained as: bw 2 g c m ea ? ? = (13) where bw is pfc control loop bandwidth and establishes it as 20hz. the error amplif ier is a trans-conductance amplifier that converts voltage to current with a 125mho output conductance. design example this section shows a design example of a 90w (19v/4.74a) adaptor. from the specification, all critical components are treated and final measurement results are given. the basic design specificati on are shown as following: ? ac input voltage range v rms : 90 ~ 264 v ac ? rated output power p o : 90 w ? minimum switching frequency f s,min : 35khz ? high regulated output voltage: 400v (at 180 ~ 264v ac ) ? low regulated output voltage: 250v (at 90 ~ 132v ac ) based on the given design guideline, the critical parameters are calculated and summarized in table 1: table 1. critical system parameters l b 530h t on,fix (90v rms ) 13.86s i pk 3.327a t on,fix (132v rms ) 6.44s n b 65t t on,fix (180v rms ) 3.46s n aux 7t t on,fix (264v rms ) 1.61s c o 68f/450v v o (v o = 250v) 14.043v c ea 1 f v o (v o = 400v) 8.77v reference circuit the complete circuit diagram is shown in figure 19 and the bill of materials for the pfc stage is shown in table 2 . table 2. bom list of pfc stage reference components reference components f1 4a/250v c2 0.33 /275v r1 510k c3 open r2 510k c4 open r3 10k c5 open r4 1m c7 0.47 f/400v r5 18.7k c8 0.47 f/400v r6 1m c11 2.2 f/50v r7 430k c12 68 f/450v r8 1m c24 104pf r13 open c25 open r14 24k c27 open r15 68k(47k) c28 open(22p) r16 10 c29 221pf r17 0 q1 2n-7002 r18 0.18 /2w q2 2sk-2482/ to-220 r55 open bd1 kbp205g r56 open zd1 zd24v r57 open d2 r860/to-220 r58 open d3 1n4148 r59 0 l1 1mh mov1 470v/7d l2 13mh tr1 055 l4 rm-10/ 530h u1 fan6961 l5 400 h c1 224pf
AN-6961 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 ? 4/8/09 8 figure 19. application circuit diagram (90w/19v) disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
|
